The present invention generally relates to mapping logic to resources in a programmable logic device, and more particularly to remapping combinations of previously mapped logic modules.
Field programmable gate arrays (FPGAs), first introduced by Xilinx, Inc. in the 1980""s, are becoming increasingly popular devices for use in electronics systems. For example, communications systems employ FPGAs in large measure for their re-programmability. In general, the use of FPGAs continues to grow at a rapid rate, because they permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility in their re-programmability. One such FPGA, the Xilinx XC4000(trademark) Series FPGA, is described in detail in pages 4-5 through 4-69 of the Xilinx 1998 Data Book entitled xe2x80x9cThe Programmable Logic Data Book 1998xe2x80x9d, published in 1998 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.)
As FPGA designs increase in complexity, they reach a point at which the designer cannot deal with the entire design at the gate level. Where once a typical FPGA design comprised perhaps 5,000 gates, FPGA designs with 50,000 gates are now common, and FPGAs supporting over 300,000 gates are available. To deal with this complexity, circuits are typically partitioned into smaller circuits that are more easily handled. Often, these smaller circuits are divided into yet smaller circuits, imposing on the design a multi-level hierarchy of logical blocks.
Libraries of pre-developed blocks of logic have been developed that can be included in an FPGA design. Such library modules include, for example, adders, multipliers, filters, and other arithmetic and DSP functions from which complex designs can be readily constructed. The use of pre-developed logic blocks permits faster design cycles by eliminating the redesign of circuits. Thus, using blocks of logic from a library may reduce design costs. However, the circuit that results when combining predefined logic blocks may have sub-optimal circuit performance and may use more resources of the programmable gate array than is desirable. Thus, the use of predefined logic blocks to lower design costs may conflict with the objectives of optimizing performance and conserving resources of the programmable gate array.
A method that address the aforementioned problems, as well as other related problems, is therefore desirable.
In various embodiments, the invention provides a method for remapping logic modules to resources of a programmable gate array. Whereas conventional methods that support reuse of logic modules are believed to provide functionally complete circuits at the expense of performance and resource usage, the present method supports logic reuse and produces circuits with enhanced performance and reduced resource requirements.
In accordance with one embodiment, connections are specified between at least two logic modules, wherein each module has a respective floorplan that includes a set of circuit elements. A first set of resources of the programmable gate array is compared to a second set of resources, wherein the second set of resources are those resources required by the sets of circuit elements. If the first set of resources covers the second set of resources (i.e., if the first set of resources includes at least the same resources as the second set), the floorplans of the logic modules are combined into a single floorplan that maps to the first set of resources.
The invention provides increased circuit performance by producing a circuit floorplan having path lengths less than the path lengths resulting from simple connections between the logic modules. In other words, combining the logic of the logic modules into a single combinational network and producing therefrom a single floorplan improves performance and reduces resource usage.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide additional example embodiments and aspects of the present invention.